 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Document Number: MCF52259 Rev. 2, 8/2009 MCF52259 LQFP-144 20 mm x 20 mm MCF52259 ColdFire Microcontroller The MCF52259 microcontroller family (MCF52252, MCF52254, MCF52255, MCF52256, MCF52258, and MCF52259 devices) is a member of the ColdFire(R) family of reduced instruction set computing (RISC) microprocessors. This document provides an overview of the 32-bit MCF52259 microcontroller, focusing on its highly integrated and diverse feature set. This 32-bit device is based on the Version 2 ColdFire core operating at a frequency up to 80 MHz, offering high performance and low power consumption. On-chip memories connected tightly to the processor core include up to 512 Kbytes of flash memory and 64 Kbytes of static random access memory (SRAM). On-chip modules include: * V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at 80 MHz running from internal flash memory with Enhanced Multiply Accumulate (MAC) Unit and hardware divider * Cryptography Acceleration Unit (CAU) * Fast Ethernet controller (FEC) * Mini-FlexBus external bus interface available on 144 pin packages * Universal Serial Bus On-The-Go (USBOTG) * USB Transceiver * FlexCAN controller area network (CAN) module * Three universal asynchronous/synchronous receiver/transmitters (UARTs) * Two inter-integrated circuit (I2CTM) bus interface modules * Queued serial peripheral interface (QSPI) module * Eight-channel 12-bit fast analog-to-digital converter (ADC) with simultaneous sampling * Four-channel direct memory access (DMA) controller * Four 32-bit input capture/output compare timers with DMA support (DTIM) * Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width modulation * * * * * * * * MAPBGA-144 13 mm x 13 mm LQFP-100 14 mm x 14 mm (PWM), pulse-code modulation (PCM), and pulse accumulation Eight-channel/Four-channel, 8-bit/16-bit pulse width modulation timer Two 16-bit periodic interrupt timers (PITs) Real-time clock (RTC) module with 32 kHz crystal Programmable software watchdog timer Secondary watchdog timer with independent clock Interrupt controller capable of handling 57 sources Clock module with 8 MHz on-chip relaxation oscillator and integrated phase-locked loop (PLL) Test access/debug port (JTAG, BDM) Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2009. All rights reserved. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Freescale Semiconductor Data Sheet: Technical Data Table of Contents 1 2 Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .26 2.4 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . .28 2.5 EzPort Electrical Specifications . . . . . . . . . . . . . . . . . .29 2.6 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .30 2.8 Clock Source Electrical Specifications . . . . . . . . . . . . .31 2.9 USB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.10 Mini-FlexBus External Interface Specifications . . . . . . .32 2.11 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . 2.12 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . 2.13 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.14 I2C Input/Output Timing Specifications . . . . . . . . . . . . 2.15 Analog-to-Digital Converter (ADC) Parameters. . . . . . 2.16 Equivalent Circuit for ADC Inputs . . . . . . . . . . . . . . . . 2.17 DMA Timers Timing Specifications . . . . . . . . . . . . . . . 2.18 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . 2.19 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 2.20 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 35 36 37 38 39 40 40 40 43 44 45 3 4 MCF52259 ColdFire Microcontroller, Rev. 2 2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages 1 Family Configurations Table 1. MCF52259 Family Configurations Module 52252 * 52254 * 52255 * up to 80 MHz1 52256 * 52258 * 52259 * up to 80 MHz1 Version 2 ColdFire Core with eMAC (Enhanced multiply-accumulate unit) and CAU (Cryptographic acceleration unit) System Clock Performance (Dhrystone 2.1 MIPS) Flash Static RAM (SRAM) Two Interrupt Controllers (INTC) Fast Analog-to-Digital Converter (ADC) USB On-The-Go (USB OTG) Mini-FlexBus external bus interface Fast Ethernet Controller (FEC) Random Number Generator and Cryptographic Acceleration Unit (CAU) FlexCAN 2.0B Module Four-channel Direct-Memory Access (DMA) Software Watchdog Timer (WDT) Secondary Watchdog Timer Two-channel Periodic Interrupt Timer (PIT) Four-Channel General Purpose Timer (GPT) 32-bit DMA Timers QSPI UART(s) I 2C up to 66 or 80 MHz1 up to 66 or 80 MHz1 up to 63 or 76 256 KB 32 KB * * * -- * -- Varies * * * 2 * 4 * 3 2 * * * * * 512 KB 64 KB * * * -- * -- Varies * * * 2 * 4 * 3 2 * * * * * 100 LQFP 512 KB 64 KB * * * -- * * * * * * 2 * 4 * 3 2 * * * * * 256 KB 32 / 64 KB * * * * * -- Varies * * * 2 * 4 * 3 2 * * * * * 512 KB 64 KB * * * * * -- Varies * * * 2 * 4 * 3 2 * * * * * 512 KB 64 KB * * * * * * * * * * 2 * 4 * 3 2 * * * * * Eight/Four-channel 8/16-bit PWM Timer General Purpose I/O Module (GPIO) Chip Configuration and Reset Controller Module Background Debug Mode (BDM) JTAG - IEEE 1149.1 Test Access Port Package 1 144 LQFP or 144 MAPBGA 66 MHz = 63 MIPS; 80 MHz = 76 MIPS MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations 1.1 Block Diagram Figure 1 shows a top-level block diagram of the device. Package options for this family are described later in this document. EzPD EzPQ EzPCK EzPCS Mini-FlexBus To/From PADI Arbiter USB Interrupt Controllers PADI - Pin Muxing USB Mini-FlexBus AN[7:0] I2Cs QSPI UARTs GPTn IRQn FEC DTINn/DTOUTn CANRX CANTX PWMn EzPort JTAG/BDM EzPort To/From PADI FEC 4 ch DMA To/From PADI UARTs 0-2 PITs 0-1 I2C 0-1 QSPI DTIMs 0-3 FlexCAN Edge Port RTC JTAG_EN MUX V2 ColdFire CPU JTAG TAP IFP OEP CAU EMAC PMM To/From PADI ADC up to 64 Kbytes SRAM (4Kx16)x4 up to 512Kbytes Flash (64Kx16)x4 PORTS (GPIO) CCM, Reset RSTIN RSTOUT VRH VRL PLL CLKGEN Watchdog Timer RNGA GPT PWM EXTAL XTAL CLKOUT Figure 1. Block Diagram 1.2 1.2.1 * Features Feature Overview Version 2 ColdFire variable-length RISC processor core -- Static operation -- 32-bit address and data paths on-chip The MCF52259 family includes the following features: MCF52259 ColdFire Microcontroller, Rev. 2 4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations * * * * * Up to 80 MHz processor core frequency 40 MHz or 33 MHz peripheral bus frequency Sixteen general-purpose, 32-bit data and address registers Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions for improved bit processing (ISA_A+) -- Enhanced Multiply-Accumulate (EMAC) unit with four 32-bit accumulators to support 16x16 32 or 32x32 48 operations -- Cryptographic Acceleration Unit (CAU) - Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions - Support for DES, 3DES, AES, MD5, and SHA-1 algorithms System debug support -- Real-time trace for determining dynamic execution path -- Background debug mode (BDM) for in-circuit debugging (DEBUG_B+) -- Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or 2-level trigger On-chip memories -- Up to 64-Kbyte dual-ported SRAM on CPU internal bus, supporting core, DMA, and USB access with standby power supply support for the first 16 Kbytes -- Up to 512 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses Power management -- Fully static operation with processor sleep and whole chip stop modes -- Rapid response to interrupts from the low-power sleep mode (wake-up feature) -- Clock enable/disable for each peripheral when not used (except backup watchdog timer) -- Software controlled disable of external clock output for low-power consumption FlexCAN 2.0B module -- Based on and includes all existing features of the Freescale TouCAN module -- Full implementation of the CAN protocol specification version 2.0B - Standard data and remote frames (up to 109 bits long) - Extended data and remote frames (up to 127 bits long) - Zero to eight bytes data length - Programmable bit rate up to 1 Mbit/sec -- Flexible message buffers (MBs), totalling up to 16 message buffers of 0-8 byte data length each, configurable as Rx or Tx, all supporting standard and extended messages -- Unused MB space can be used as general purpose RAM space -- Listen-only mode capability -- Content-related addressing -- No read/write semaphores -- Three programmable mask registers: global for MBs 0-13, special for MB14, and special for MB15 -- Programmable transmit-first scheme: lowest ID or lowest buffer number -- Time stamp based on 16-bit free-running timer -- Global network time, synchronized by a specific message -- Maskable interrupts Universal Serial Bus On-The-Go (USB OTG) dual-mode host and device controller -- Full-speed / low-speed host controller -- USB 1.1 and 2.0 compliant full-speed / low speed device controller -- 16 bidirectional end points MCF52259 ColdFire Microcontroller, Rev. 2 -- -- -- -- Freescale Semiconductor 5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations * -- DMA or FIFO data stream interfaces -- Low power consumption -- OTG protocol logic Fast Ethernet controller (FEC) -- 10/100 BaseT/TX capability, half duplex or full duplex -- On-chip transmit and receive FIFOs -- Built-in dedicated DMA controller -- Memory-based flexible descriptor rings * * * * * Mini-FlexBus -- External bus interface available on 144 pin packages -- Supports glueless interface with 8-bit ROM/flash/SRAM/simple slave peripherals. Can address up to 2 Mbytes of addresses -- 2 chip selects (FB_CS[1:0]) -- Non-multiplexed mode: 8-bit dedicated data bus, 20-bit address bus -- Multiplexed mode: 16-bit data and 20-bit address bus -- FB_CLK output to support synchronous memories -- Programmable base address, size, and wait states to support slow peripherals -- Operates at up to 40 MHz (bus clock) in 1:2 mode or up to 80 MHz (core clock) in 1:1 mode Three universal asynchronous/synchronous receiver transmitters (UARTs) -- 16-bit divider for clock generation -- Interrupt control logic with maskable interrupts -- DMA support -- Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity -- Up to two stop bits in 1/16 increments -- Error-detection capabilities -- Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs -- Transmit and receive FIFO buffers Two I2C modules -- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads -- Fully compatible with industry-standard I2C bus -- Master and slave modes support multiple masters -- Automatic interrupt generation with programmable level Queued serial peripheral interface (QSPI) -- Full-duplex, three-wire synchronous transfers -- Up to three chip selects available -- Master mode operation only -- Programmable bit rates up to half the CPU clock frequency -- Up to 16 pre-programmed transfers Fast analog-to-digital converter (ADC) -- Eight analog input channels -- 12-bit resolution -- Minimum 1.125 s conversion time -- Simultaneous sampling of two channels for motor control applications -- Single-scan or continuous operation -- Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit MCF52259 ColdFire Microcontroller, Rev. 2 6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations * * * * * * * * -- Unused analog channels can be used as digital I/O Four 32-bit timers with DMA support -- 12.5 ns resolution at 80 MHz -- Programmable sources for clock input, including an external clock option -- Programmable prescaler -- Input capture capability with programmable trigger edge on input pin -- Output compare with programmable mode for the output pin -- Free run and restart modes -- Maskable interrupts on input capture or output compare -- DMA trigger capability on input capture or output compare Four-channel general purpose timer -- 16-bit architecture -- Programmable prescaler -- Output pulse-widths variable from microseconds to seconds -- Single 16-bit input pulse accumulator -- Toggle-on-overflow feature for pulse-width modulator (PWM) generation -- One dual-mode pulse accumulation channel Pulse-width modulation timer -- Support for PCM mode (resulting in superior signal quality compared to conventional PWM) -- Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution -- Programmable period and duty cycle -- Programmable enable/disable for each channel -- Software selectable polarity for each channel -- Period and duty cycle are double buffered. Change takes effect when the end of the current period is reached (PWM counter reaches zero) or when the channel is disabled. -- Programmable center or left aligned outputs on individual channels -- Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies -- Emergency shutdown Two periodic interrupt timers (PITs) -- 16-bit counter -- Selectable as free running or count down Real-Time Clock (RTC) -- Maintains system time-of-day clock -- Provides stopwatch and alarm interrupt functions -- Standby power supply (Vstby) keeps the RTC running when the system is shut down Software watchdog timer -- 32-bit counter -- Low-power mode support Backup watchdog timer (BWT) -- Independent timer that can be used to help software recover from runaway code -- 16-bit counter -- Low-power mode support Clock generation features -- Twelve to 48 MHz crystal, 8 MHz on-chip trimmed relaxation oscillator, or external oscillator reference options -- Two to 10 MHz reference frequency for normal PLL mode with a pre-divider programmable from 1 to 8 MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations * * * * * * -- System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator -- Low power modes supported -- 2n (n 0 15) low-power divider for extremely low frequency operation Interrupt controller -- Uniquely programmable vectors for all interrupt sources -- Fully programmable level and priority for all peripheral interrupt sources -- Seven external interrupt signals with fixed level and priority -- Unique vector number for each interrupt source -- Ability to mask any individual interrupt source or all interrupt sources (global mask-all) -- Support for hardware and software interrupt acknowledge (IACK) cycles -- Combinatorial path to provide wake-up from low-power modes DMA controller -- Four fully programmable channels -- Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4x32-bit) burst transfers -- Source/destination address pointers that can increment or remain constant -- 24-bit byte transfer counter per channel -- Auto-alignment transfers supported for efficient block movement -- Bursting and cycle-steal support -- Software-programmable DMA requests for the UARTs (3) and 32-bit timers (4) -- Channel linking support Reset -- Separate reset in and reset out signals -- Seven sources of reset: - Power-on reset (POR) - External - Software - Watchdog - Loss of clock / loss of lock - Low-voltage detection (LVD) - JTAG -- Status flag indication of source of last reset Chip configuration module (CCM) -- System configuration during reset -- Selects one of six clock modes -- Configures output pad drive strength -- Unique part identification number and part revision number General purpose I/O interface -- Up to 56 bits of general purpose I/O on 100-pin package -- Up to 96 bits of general purpose I/O on 144-pin package -- Bit manipulation supported via set/clear functions -- Programmable drive strengths -- Unused peripheral pins may be used as extra GPIO JTAG support for system level board testing MCF52259 ColdFire Microcontroller, Rev. 2 8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations 1.2.2 V2 Core Overview The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed. The V2 core implements the ColdFire instruction set architecture revision A+ with support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the core includes the enhanced multiply-accumulate (EMAC) unit for improved signal processing capabilities. The EMAC implements a three-stage arithmetic pipeline, optimized for 32x32 bit operations, with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The EMAC provides support for execution of DSP operations within the context of a single processor at a minimal hardware cost. 1.2.3 Integrated Debug Module The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator development tools. Through a standard debug interface, access to debug information and real-time tracing capability is provided on 144-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register, a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the dedicated debug serial communication channel or from the processor's supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. This device implements revision B+ of the ColdFire Debug Architecture. The processor's interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event. This ensures the system continues to operate even during debugging. To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at the CPU's clock rate. The device includes a new debug signal, ALLPST. This signal is the logical AND of the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111). The full debug/trace interface is available only on the 144-pin packages. However, every product features the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal. 1.2.4 JTAG The processor supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a boundary-scan register, and a 32-bit ID register). The boundary scan register links the device's pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic. The device implementation can: * * * * * Perform boundary-scan operations to test circuit board electrical continuity Sample system pins during operation and transparently shift out the result in the boundary scan register Bypass the device for a given circuit board test by effectively reducing the boundary-scan register to a single bit Disable the output drive to pins during circuit-board testing Drive output pins to stable levels MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations 1.2.5 1.2.5.1 On-Chip Memories SRAM The dual-ported SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 64-Kbyte boundary within the 4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. The SRAM module is also accessible by the DMA, FEC, and USB. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance. 1.2.5.2 Flash Memory The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor's high-speed local bus. The CFM is constructed with four banks of 64-Kbytex16-bit flash memory arrays to generate 512 Kbytes of 32-bit flash memory. These electrically erasable and programmable arrays serve as non-volatile program and data memory. The flash memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without requiring an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller that supports interleaved accesses from the 2-cycle flash memory arrays. A backdoor mapping of the flash memory is used for all program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also be programmed via the EzPort, which is a serial flash memory programming interface that allows the flash memory to be read, erased and programmed by an external controller in a format compatible with most SPI bus flash memory chips. 1.2.6 Cryptographic Acceleration Unit The MCF52235 device incorporates two hardware accelerators for cryptographic functions. First, the CAU is a coprocessor tightly-coupled to the V2 ColdFire core that implements a set of specialized operations to increase the throughput of software-based encryption and message digest functions, specifically the DES, 3DES, AES, MD5 and SHA-1 algorithms. Second, a random number generator provides FIPS-140 compliant 32-bit values to security processing routines. Both modules supply critical acceleration to software-based cryptographic algorithms at a minimal hardware cost. 1.2.7 Power Management The device incorporates several low-power modes of operation entered under program control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD) monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the chip falls below the standby battery voltage. 1.2.8 FlexCAN The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of FlexCAN has 16 message buffers. MCF52259 ColdFire Microcontroller, Rev. 2 10 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations 1.2.9 Mini-FlexBus A multi-function external bus interface called the Mini-FlexBus is provided on the device with basic functionality of interfacing to slave-only devices with a maximum slave bus frequency up to 40 MHz in 1:2 mode and 80 MHz in 1:1 mode. It can be directly connected to the following asynchronous or synchronous devices with little or no additional circuitry: * * * * External ROMs Flash memories Gate-array logic Other simple target (slave) devices The Mini-FlexBus is a subset of the FlexBus module found on higher-end ColdFire microprocessors. The Mini-FlexBus minimizes package pin-outs while maintaining a high level of configurability and functionality. 1.2.10 USB On-The-Go Controller The device includes a Universal Serial Bus On-The-Go (USB OTG) dual-mode controller. USB is a popular standard for connecting peripherals and portable consumer electronic devices such as digital cameras and handheld computers to host PCs. The OTG supplement to the USB specification extends USB to peer-to-peer application, enabling devices to connect directly to each other without the need for a PC. The dual-mode controller on the device can act as a USB OTG host and as a USB device. It also supports full-speed and low-speed modes. 1.2.11 Fast Ethernet Controller (FEC) The Ethernet media access controller (MAC) supports 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports three different standard MAC-PHY (physical) interfaces for connection to an external Ethernet transceiver. The FECs supports the 10/100 Mbps MII, and the 10 Mbps-only 7-wire interface. 1.2.12 UARTs The device has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital I/O functions. 1.2.13 I2C Bus The processor includes two I2C modules. The I2C bus is an industry-standard, two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. 1.2.14 QSPI The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPU intervention between transfers. 1.2.15 Fast ADC The fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing. Signals on the SYNCA and SYNCB pins initiate an ADC conversion. MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations The ADC can be configured to perform a single scan and halt, a scan when triggered, or a programmed scan sequence repeatedly until manually stopped. The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled. During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This configuration requires that a single channel may not be sampled by both S/H circuits simultaneously. Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions. 1.2.16 DMA Timers (DTIM0-DTIM3) There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the device. Each module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTINn signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler that clocks the actual timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode. Timer events may optionally cause interrupt requests or DMA transfers. 1.2.17 General Purpose Timer (GPT) The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable counter driven by a seven-stage programmable prescaler. Each of the four channels can be configured for input capture or output compare. Additionally, channel three, can be configured as a pulse accumulator. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. The input capture and output compare functions allow simultaneous input waveform measurements and output waveform generation. The input capture function can capture the time of a selected transition edge. The output compare function can generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator. 1.2.18 Periodic Interrupt Timers (PIT0 and PIT1) The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular intervals with minimal processor intervention. Each timer can count down from the value written in its PIT modulus register or it can be a free-running down-counter. 1.2.19 Real-Time Clock (RTC) The Real-Time Clock (RTC) module maintains the system (time-of-day) clock and provides stopwatch, alarm, and interrupt functions. It includes full clock features: seconds, minutes, hours, days and supports a host of time-of-day interrupt functions along with an alarm interrupt. 1.2.20 Pulse-Width Modulation (PWM) Timers The device has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty cycle as well as a dedicated counter. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The timer supports PCM mode, which results in superior signal quality when compared to that of a conventional PWM. The PWM outputs have programmable polarity, and can be programmed as left aligned outputs or center aligned outputs. For MCF52259 ColdFire Microcontroller, Rev. 2 12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels. 1.2.21 Software Watchdog Timer The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown. 1.2.22 Backup Watchdog Timer The backup watchdog timer is an independent 16-bit timer that, like the software watchdog timer, facilitates recovery from runaway code. This timer is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown. The backup watchdog timer can be clocked by either the relaxation oscillator or the system clock. 1.2.23 Phase-Locked Loop (PLL) The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control logic. To improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS. 1.2.24 Interrupt Controllers (INTCn) The device has two interrupt controllers that supports up to 128 interrupt sources. There are 56 programmable sources, 49 of which are assigned to unique peripheral interrupt requests. The remaining seven sources are unassigned and may be used for software interrupt requests. 1.2.25 DMA Controller The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events. 1.2.26 * * * * * * * Reset The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what caused the last reset. There are seven sources of reset: External reset input Power-on reset (POR) Watchdog timer Phase locked-loop (PLL) loss of lock / loss of clock Software Low-voltage detector (LVD) JTAG Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other registers provide status flags indicating the last source of reset and a control bit for software assertion of the RSTO pin. MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations 1.2.27 GPIO Nearly all pins on the device have general purpose I/O capability and are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pin. 1.2.28 Part Numbers and Packaging This product is RoHS-compliant. Refer to the product page at freescale.com or contact your sales office for up-to-date RoHS information. Table 2. Orderable Part Number Summary Freescale Part Number MCF52252AF80 MCF52252CAF66 MCF52254AF80 MCF52254CAF66 MCF52255CAF80 MCF52256AG80 MCF52256CAG66 MCF52256CVN66 MCF52256VN80 MCF52258AG80 MCF52258CAG66 MCF52258CVN66 MCF52258VN80 MCF52259CAG80 MCF52259CVN80 MCF52268AG80 MCF52268VN80 FlexCAN -- * -- * * -- * * -- -- * * -- * * -- -- Encryption -- -- -- -- * -- -- -- -- -- -- -- -- * * -- 80 -- 512 64 144 MAPBGA 0 to +70 80 512 64 144 MAPBGA 144 LQFP -40 to +85 0 to +70 Speed (MHz) 80 256 66 80 512 66 80 80 66 256 66 80 80 144 LQFP 66 512 66 144 MAPBGA 80 144 LQFP 0 to +70 -40 to +85 64 -40 to +85 -40 to +85 64 144 MAPBGA 32 0 to +70 0 to +70 -40 to +85 512 64 32 144 LQFP 64 -40 to +85 100 LQFP 64 100 LQFP -40 to +85 -40 to +85 0 to +70 32 100 LQFP -40 to +85 0 to +70 Flash (Kbytes) SRAM (Kbytes) Package Temp range (C) 0 to +70 MCF52259 ColdFire Microcontroller, Rev. 2 14 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations RTC_XTAL FB_D4 FB_A10 FB_A11 FB_A12 FB_A13 FB_A14 URXD0 UCTS0 UTXD0 TEST URTS0 QSD0 SCL TIN1 RTC_EXTAL FB_A5 VSS RCON QSDI VDD PCS0 PCS2 PCS3 VDD SDA SCK VDD TIN3 TIN0 VSS VSS 7 1 8 9 6 5 4 3 2 FB_A6 FB_A7 FB_A8 FB_A9 * 12 11 14 18 17 16 13 15 10 19 30 20 28 21 31 24 25 29 26 36 27 23 22 FB_ALE TMS TRST TDI TDO ALLPST TCLK JTAG_EN FB_RW FB_D3 FB_D2 VDD VSS FB_D1 FB_D0 FB_CS0 FB_A4 FB_A3 FB_A2 FB_A1 FB_A0 ICOC3 VDD VSS UCTS1 UTXD1 URXD1 URTS1 TIN2 AN0 AN1 AN2 AN3 VSSA VRL VRH 70 71 72 102 108 104 101 105 107 103 100 97 106 95 91 94 98 99 90 92 93 96 78 87 88 89 80 81 79 83 84 85 86 73 74 75 76 77 82 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 35 34 33 32 CLKMOD1 CLKMOD0 RSTOUT RSTIN FB_D5 FB_D6 FB_D7 FB_OE FB_A15 VDD VSS FB_A16 FB_A17 FB_A18 FB_A19 IRQ3 IRQ5 FEC_RXD3 FEC_RXD2 VDD VSS FEC_RXD1 FEC_RXD0 FEC_RXDV FEC_RXCLK FEC_RXER FEC_TXER FEC_TXCLK FEC_TXEN VDD VSS FEC_TXD0 FEC_TXD1 FEC_TXD2 FEC_TXD3 FEC_COL Figure 2 shows the pinout configuration for the 144 LQFP. Freescale Semiconductor Figure 2. 144 LQFP Pin Assignment MCF52259 ColdFire Microcontroller, Rev. 2 VSS VSS VDD IRQ7 PST0 PST3 PST2 PST1 AN7 AN6 AN5 AN4 ICOC2 UCTS2 ICOC1 URTS2 ICOC0 VSTBY DDATA0 DDATA1 DDATA2 DDATA3 USB_DP USB_DM VDDUSB VDDA VSSUSB XTAL IRQ1 Family Configurations URXD2 UTXD2 VDD EXTAL FEC_CRS VSSPLL VDDPLL 15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations Figure 3 shows the pinout configuration for the 100 LQFP. 16 VDD VSS TEST RCON TIN0 TIN1 RTC_EXTAL RTC_XTAL UCTS0 UTXD0 URXD0 URTS0 TIN3 VDD VSS PCS3 PCS2 QSDI QSDO SCK PCS0 SCL SDA VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 LQFP Figure 3. 100 LQFP Pin Assignments MCF52259 ColdFire Microcontroller, Rev. 2 TMS TRST TDI TDO ALLPST TCLK JTAG_EN VDD VSS ICOC3 VDD VSS UCTS1 UTXD1 URXD1 URTS1 TIN2 AN0 AN1 AN2 AN3 VSSA VRL VRH VDDA 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 FEC_CRS VDDPLL EXTAL XTAL VSSPLL IRQ1 URXD2 UTXD2 VDD VSS URTS2 UCTS2 IRQ7 ICOC2 ICOC1 ICOC0 VSSUSB USB_DP USB_DM VDDUSB VSTBY AN4 AN5 AN6 AN7 CLKMOD1 CLKMOD0 RSTOUT RSTIN IRQ3 IRQ5 FEC_RXD3 FEC_RXD2 VDD VSS FEC_RXD1 FEC_RXD0 FEC_RXDV FEC_RXCLK FEC_RXER FEC_TXER FEC_TXCLK FEC_TXEN VDD VSS FEC_TXD0 FEC_TXD1 FEC_TXD2 FEC_TXD3 FEC_COL Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Figure 4 shows the pinout configuration for the 144 MAPBGA. 1 A VSS 2 RSTOUT 3 RSTIN 4 FB_D6 5 FB_D7 6 IRQ3 7 IRQ5 8 FEC_ RXD0 FEC_ RXCLK FEC_ RXDV FEC_ TXER 9 FEC_ RXER FEC_ TXCLK FEC_ TXD1 FEC_ TXD0 10 FEC_ TXEN FEC_ TXD2 11 FEC_ TXD3 12 VSS A B TEST FB_A14 FB_D4 FB_D5 FB_OE FB_A19 FEC_ RXD1 FEC_ RXD2 FEC_ RXD3 FEC_COL FEC_CRS B C TIN1 FB_A12 FB_A13 FB_A15 FB_A16 FB_A18 URXD2 VDDPLL EXTAL C D RTC_ EXTAL RTC_ XTAL TIN0 FB_A11 CLKMOD1 CLKMOD0 FB_A17 UTXD2 VSSPLL XTAL D E UCTS0 FB_A10 RCON VDD VDD VDD VDD IRQ1 URTS2 UCTS2 IRQ7 E F UTXD0 URXD0 URTS0 TIN3 VDD VSS VSS VSS PST3 DDATA0 DDATA1 ICOC0 F G QSDO QSDI PCS2 PCS3 VDD VSS VSS VSS DDATA3 PST2 PST1 PST0 G H SCL SDA SCK PCS0 VDD VDD VDD VSS VSSUSB DDATA2 USB_DM USB_DP H J FB_A6 FB_A7 FB_A9 FB_A8 FB_D0 FB_A3 VDD TIN2 VDDUSB ICOC2 ICOC1 VSTBY J K TMS TRST FB_ALE FB_A5 FB_D2 FB_A4 UCTS1 UTXD1 AN3 AN6 AN4 AN5 K L TDI TDO ALLPST FB_D3 FB_D1 FB_A1 FB_A0 URXD1 AN2 VRH VDDA AN7 L M VSS 1 JTAG_ EN 2 TCLK 3 FB_RW 4 FB_CS0 5 FB_A2 6 ICOC3 7 URTS1 8 AN0 9 AN1 10 VRL 11 VSSA 12 M Figure 4. Pinout Top View (144 MAPBGA) MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 17 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations Table 3 shows the pin functions by primary and alternate purpose, and illustrates which packages contain each pin. Table 3. Pin Functions by Primary and Alternate Purpose Pin Group ADC Primary Function AN[7:0] Secondary Tertiary Quaternary Function Function Function (Alt 2) (GPIO) (Alt 1) -- -- PAN[7:0] Slew Rate Low Drive Pull-up/ Pin on Strength/Co Pull-down2 144 MAPBGA 1 ntrol Low -- L12, K10, K12, K11, K9, L9, M10, M9 L11 M12 L10 M11 C12 D12 C11 D11 D1 E1 L3 G9, H10, F11, F10 F9, G10, G11, G12 Pin on 144 LQFP 74-77; 69, 68, 67 ,66 73 70 72 71 106 105 107 104 13 14 42 86, 85, 84, 83 87-90 Pin on 100 LQFP 51-54, 46, 45, 44, 43 50 47 49 48 73 72 74 71 7 8 30 -- -- Family Configurations 18 MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor VDDA VSSA VRH VRL Clock Generation EXTAL XTAL VDDPLL VSSPLL RTC RTC_EXTAL RTC_XTAL Debug Data ALLPST DDATA[3:0] PST[3:0] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PDD[7:4] PDD[3:0] N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Low Low Low N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A High High High -- -- -- -- -- -- -- -- -- -- -- -- -- Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Table 3. Pin Functions by Primary and Alternate Purpose (continued) Pin Group FEC Primary Function FEC_COL FEC_CRS FEC_RXCLK FEC_RXD[3:0] FEC_RXDV FEC_RXER FEC_TXCLK FEC_TXD[3:0] FEC FEC_TXEN FEC_TXER I 2C03 Freescale Semiconductor MCF52259 ColdFire Microcontroller, Rev. 2 19 Secondary Tertiary Quaternary Function Function Function (Alt 1) (Alt 2) (GPIO) -- -- -- -- -- -- -- -- -- -- -- -- -- FEC_MDC FEC_MDIO -- -- -- -- -- -- -- -- -- -- -- -- -- UTXD2 URXD2 -- -- -- USB_ALT CLK -- FB_CLK PTI0 PTI1 PTI2 PTI[3:6] PTI7 PTJ0 PTJ1 PTJ[2:5] PTJ6 PTJ7 PAS0 PAS1 PNQ7 PNQ5 PNQ3 PNQ1 -- -- Slew Rate PSRRH[0] PSRRH[1] PSRRH[2] PSRRH[6:3] PSRRH[7] PSRRH[8] PSRRH[9] Drive Pull-up/ Pin on Strength/Co Pull-down2 144 MAPBGA ntrol1 PDSRH[0] PDSRH[1] PDSRH[2] PDSRH[6:3] PDSRH[7] PDSRH[8] PDSRH[9] -- -- -- -- -- -- -- -- -- -- Pull-Up4 Pull-Up4 Pull-Up4 Pull-Up 4 4 Pin on 144 LQFP 109 108 120 127, 126, 123, 122 121 119 117 110-113 116 118 28 29 96 128 129 103 44 43 Pin on 100 LQFP 76 75 87 94, 93, 90, 89 88 86 84 77, 78, 79, 80 83 85 22 23 63 95 96 70 32 31 Family Configurations B11 B12 B8 D7, C7, B7, A8 C8 A9 B9 A11, B10, C9, D9 A10 D8 H1 H2 E12 A7 A6 E9 M2 M3 PSRRH[13:10] PDSRH[13:1 0] PSRRH[14] PSRRH[15] PSRR[0] PSRR[0] Low Low Low Low N/A Low PDSRH[14] PDSRH[15] PDSR[0] PDSR[0] Low Low Low High N/A Low I2C_SCL0 I2C_SDA0 Interrupts IRQ7 IRQ5 IRQ3 IRQ1 Pull-Up Pull-Up4 Pull-Down Pull-Up5 JTAG/BDM JTAG_EN TCLK/ PSTCLK/ CLKOUT TDI/DSI TDO/DSO TMS/BKPT TRST/DSCLK -- -- -- -- -- -- -- -- -- -- -- -- N/A Low N/A N/A N/A Low N/A N/A Pull-Up5 -- Pull-Up Pull-Up 5 5 L1 L2 K1 K2 40 41 38 39 28 29 26 27 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Table 3. Pin Functions by Primary and Alternate Purpose (continued) Pin Group Mode Selection QSPI Primary Function RCON/EZPCS CLKMOD[1:0] QSPI_CS3 QSPI_CS2 Secondary Tertiary Quaternary Function Function Function (Alt 1) (Alt 2) (GPIO) -- -- SYNCA SYNCB -- -- USB_DP_ PDOWN USB_DM _ PDOWN UCTS1 URTS1 URXD1 UTXD1 -- -- -- PWM7 PWM5 PWM3 PWM1 PWM6 PWM4 -- -- PQS6 PQS5 Slew Rate N/A N/A PSRR[7] PSRR[6] Drive Pull-up/ Pin on Strength/Co Pull-down2 144 MAPBGA ntrol1 N/A N/A PDSR[7] PDSR[6] Pull-Up Pull-Down -- -- E4 D4, D5 G4 G3 Pin on 144 LQFP 10 144, 143 22 23 Pin on 100 LQFP 4 100, 99 16 17 Family Configurations 20 MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor QSPI_CS0 QSPI_CLK/ EZPCK QSPI QSPI_DIN/ EZPD Reset7 RSTI RSTO Test Timer 3, 16-bit Timer 2, 16-bit Timer 1, 16-bit Timer 0, 16-bit Timer 3, 32-bit Timer 2, 32-bit TEST GPT3 GPT2 GPT1 GPT0 DTIN3 DTIN2 I2C_SDA0 I2C_SCL0 I2C_SDA1 PQS3 PQS2 PQS1 PQS0 -- -- -- PTA3 PTA2 PTA1 PTA0 PTC3 PTC2 PSRR[4] PSRR[3] PSRR[2] PSRR[1] N/A Low N/A PSRR[23] PSRR[22] PSRR[21] PSRR[20] PSRR[19] PSRR[18] PDSR[4] PDSR[3] PDSR[2] PDSR[1] N/A High N/A PDSR[23] PDSR[22] PDSR[21] PDSR[20] PDSR[19] PDSR[18] Pull-Up6 Pull-Up6 Pull-Up6 Pull-Up6 Pull-Up7 -- Pull-Down Pull-Up8 Pull-Up8 Pull-Up8 Pull-Up8 -- -- H4 H3 G2 G1 A3 A2 B1 M7 J10 J11 F12 F4 J8 27 26 24 25 141 142 9 58 95 94 93 19 65 21 20 18 19 97 98 3 35 62 61 60 13 42 QSPI_DOUT/E I2C_SCL1 ZPQ -- -- -- -- -- -- -- DTOUT3 DTOUT2 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Table 3. Pin Functions by Primary and Alternate Purpose (continued) Pin Group Timer 1, 32-bit Timer 0, 32-bit UART 0 Primary Function DTIN1 DTIN0 UCTS0 URTS0 MCF52259 ColdFire Microcontroller, Rev. 2 URXD0 UTXD0 UART 1 UCTS1 URTS1 URXD1 UTXD1 UART 2 UCTS2 Secondary Tertiary Quaternary Function Function Function (Alt 1) (Alt 2) (GPIO) DTOUT1 DTOUT0 -- -- -- -- SYNCA SYNCB I2C_SDA1 I2C_SCL1 I2C_SCL1 PWM2 PWM0 USB_VBU SE USB_VBU SD -- -- URXD2 UTXD2 -- -- USB_ VBUSCH G USB_ VBUSDIS -- -- -- -- -- -- PTC1 PTC0 PUA3 PUA2 PUA1 PUA0 PUB3 PUB2 PUB1 PUB0 PUC3 Slew Rate PSRR[17] PSRR[16] PSRR[11] PSRR[10] PSRR[9] PSRR[8] PSRR[15] PSRR[14] PSRR[13] PSRR[12] PSRR[27] Drive Pull-up/ Pin on Strength/Co Pull-down2 144 MAPBGA ntrol1 PDSR[17] PDSR[16] PDSR[11] PDSR[10] PDSR[9] PDSR[8] PDSR[15] PDSR[14] PDSR[13] PDSR[12] PDSR[27] -- -- -- -- -- -- -- -- Pull-Up6 Pull-Up6 Pull-Up6 C1 D2 E2 F3 F2 F1 K7 M8 L8 K8 E11 Pin on 144 LQFP 12 11 15 18 17 16 61 64 63 62 97 Pin on 100 LQFP 6 5 9 12 11 10 38 41 40 39 64 Freescale Semiconductor 21 URTS2 URXD2 UTXD2 USB OTG USB_DM USB_DP USB_VDD USB_VSS I2C_SDA1 CANRX CANTX -- -- -- -- PUC2 PUC1 PUC0 -- -- -- -- PSRR[26] PSRR[25] PSRR[24] N/A N/A N/A N/A PDSR[26] PDSR[25] PDSR[24] N/A N/A N/A N/A Pull-Up6 -- -- -- -- -- -- E10 C10 D10 H11 H12 J9 H9 98 102 101 80 81 79 82 65 69 68 57 58 Family Configurations 56 59 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Table 3. Pin Functions by Primary and Alternate Purpose (continued) Pin Group MiniFlexBus9 Primary Function FB_ALE FB_AD[7:0] FB_AD[15:8] Secondary Tertiary Quaternary Function Function Function (Alt 1) (Alt 2) (GPIO) FB_CS1 -- -- -- -- -- PAS2 PTE[7:0] PTF[7:0] Slew Rate PSRRL[20] PSRRL[7:0] PSRRL[15:8] Drive Pull-up/ Pin on Strength/Co Pull-down2 144 MAPBGA ntrol1 PDSRL[20] PDSRL[7:0] PDSRL[15:8] -- -- -- K3 J2, J1, K4, K6, J6, M6, L6, L7 C4, B2, C3, C2, D3, E3, J3, J4 B6, C6, D6, C5 M5 M4 B5 A5 A4 B4 B3 L4 K5 L5 J5 J12 E5-E8; F5; G5; H5-7; J7 Pin on 144 LQFP 37 34-36; 53-57 136, 2-6, 32-33 130-133 52 45 137 138 139 140 1 46 47 50 51 78 7; 20; 30; 48; 59; 92; 100; 115; 125; 135 Pin on 100 LQFP -- -- -- Family Configurations 22 FB_AD[19:16] MCF52259 ColdFire Microcontroller, Rev. 2 Standby Voltage VDD10 Freescale Semiconductor FB_CS0 FB_R/W FB_OE FB_D7 FB_D6 FB_D5 FB_D4 FB_D3 FB_D2 FB_D1 FB_D0 VSTBY VDD -- -- -- -- CANRX CANTX I2C_SCL1 I2C_SDA1 USB_ VBUSD USB_ VBUSE SYNCA SYNCB -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PTG[3:0] PTG5 PTG7 PTG6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 PTH7 PTH6 -- -- PSRRL[19:16] PDSRL[19:16 ] PSRRL[21] PSRRL[31] PSRRL[30] PSRRL[29] PSRRL[28] PSRRL[27] PSRRL[26] PSRRL[25] PSRRL[24] PSRRL[23] PSRRL[22] N/A N/A PDSRL[21] PDSRL[31] PDSRL[30] PDSRL[29] PDSRL[28] PDSRL[27] PDSRL[26] PDSRL[25] PDSRL[24] PDSRL[23] PDSRL[22] N/A N/A -- -- -- -- -- -- Pull-Up6 Pull-Up6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 55 1; 14; 24; 33; 36; 67; 82; 92 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Table 3. Pin Functions by Primary and Alternate Purpose (continued) Pin Group VSS Primary Function VSS Secondary Tertiary Quaternary Function Function Function (Alt 1) (Alt 2) (GPIO) -- -- -- Slew Rate N/A Drive Pull-up/ Pin on Strength/Co Pull-down2 144 MAPBGA ntrol1 N/A -- A1; A12; F6-8; G6-8; H8; M1; M2 Pin on 144 LQFP 8; 21; 31; 49; 60; 91; 99; 114; 124; 134 Pin on 100 LQFP 2; 15; 25; 34; 37; 66; 81; 91 Freescale Semiconductor MCF52259 ColdFire Microcontroller, Rev. 2 23 1 2 The PDSR and PSSR registers are part of the GPIO module. All programmable signals default to 2mA drive in normal (single-chip) mode. All signals have a pull-up in GPIO mode. 3 I2C1 is multiplexed with specific pins of the QSPI, UART1, UART2, and Mini-FlexBus pin groups. 4 For primary and GPIO functions only. 5 Only when JTAG mode is enabled. 6 For secondary and GPIO functions only. 7 RSTI has an internal pull-up resistor; however, the use of an external resistor is strongly recommended. 8 For GPIO functions, the Primary Function has pull-up control within the GPT module. 9 Available on 144-pin packages only. 10 This list for power and ground does not include those dedicated power/ground pins included elsewhere, such as in the ADC, USB, and PLL. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Family Configurations 2 Electrical Characteristics NOTE The parameters specified in this data sheet supersede any values found in the module specifications. This section contains electrical specification tables and reference timing diagrams for the microcontroller unit, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. 2.1 Maximum Ratings Table 4. Absolute Maximum Ratings1, 2 Rating Supply voltage Clock synthesizer supply voltage RAM standby supply voltage USB standby supply voltage Digital input voltage 3 EXTAL pin voltage XTAL pin voltage Instantaneous maximum current Single pin limit (applies to all pins)4, 5 Operating temperature range (packaged) Storage temperature range 1 Symbol VDD VDDPLL VSTBY VDDUSB VIN VEXTAL VXTAL IDD TA (TL - TH) Tstg Value -0.3 to +4.0 -0.3 to +4.0 +1.8 to 3.5 -0.3 to +4.0 -0.3 to +4.0 0 to 3.3 0 to 3.3 25 -40 to 85 or 0 to 706 -65 to 150 Unit V V V V V V V mA C C 2 3 4 5 6 Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (VSS or VDD). Input must be current limited to the IDD value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. All functional non-supply pins are internally clamped to VSS and VDD. The power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in the external power supply going out of regulation. Ensure that the external VDD load shunts current greater than maximum injection current. This is the greatest risk when the MCU is not consuming power (e.g., no clock). Depending on the packaging; see the orderable part number summary. MCF52259 ColdFire Microcontroller, Rev. 2 24 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics 2.2 Current Consumption Table 5. Typical Active Current Consumption Specifications Characteristic Symbol IDD Typical1 Active (SRAM) 22 31 84 102 ISTBY -- -- 23 -- -- Typical1 Active (Flash) 30 45 100 118 Peak2 (Flash) 36 60 155 185 5 20 15 2 6 4 Unit mA PLL @ 8 MHz PLL @ 16 MHz PLL @ 64 MHz PLL @ 80 MHz RAM standby supply current * Normal operation: VDD > VSTBY - 0.3 V * Standby operation: VDD < VSS + 0.5 V Analog supply current * Normal operation USB supply current PLL supply current 1 A A mA mA mA IDDA IDDUSB IDDPLL Tested at room temperature with CPU polling a status register. All clocks were off except the UART and CFM (when running from flash memory). 2 Peak current measured with all modules active, CPU polling a status register, and default drive strength with matching load. 3 Tested using Auto Power Down (APD), which powers down the ADC between conversions; ADC running at 4 MHz in Once Parallel mode with a sample rate of 3 kHz. 4 Tested with the PLL MFD set to 7 (max value). Setting the MFD to a lower value results in lower current consumption. Table 6. Current Consumption in Low-Power Mode, Code From Flash Memory1,2,3 Mode Stop mode 3 (Stop 11)4 Stop mode 2 (Stop 10)4 9 9 21 23 10 10 32 36 8 MHz (Typ) 16 MHz (Typ) 64 MHz (Typ) 80 MHz (Typ) Unit Symbol 0.150 7.0 15 15 56 70 17 17 65 81 mA IDD Stop mode 1 (Stop 01)4,5 Stop mode 0 (Stop Wait / Doze Run 1 2 00)5 All values are measured with a 3.30V power supply. Tests performed at room temperature. Refer to the Power Management chapter in the MCF52259 Reference Manual for more information on low-power modes. 3 CLKOUT, PST/DDATA signals, and all peripheral clocks except UART0 and CFM off before entering low-power mode. CLKOUT is disabled. 4 See the description of the Low-Power Control Register (LPCR) in the MCF52259 Reference Manual for more information on stop modes 0-3. 5 Results are identical to STOP 00 for typical values because they only differ by CLKOUT power consumption. CLKOUT is already disabled in this instance prior to entering low-power mode. MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 25 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics Table 7. Current Consumption in Low-Power Mode, Code From SRAM1,2,3 Mode Stop mode 3 (Stop 11) 4 8 MHz (Typ) 16 MHz (Typ) 64 MHz (Typ) 80 MHz (Typ) Unit Symbol 0.090 7 9 9 13 16 10 10 18 21 15 15 42 55 17 17 50 65 mA IDD Stop mode 2 (Stop 10)4 Stop mode 1 (Stop 01) Stop mode 0 (Stop 00) Wait / Doze Run 1 2 4,5 5 All values are measured with a 3.30V power supply. Tests performed at room temperature. Refer to the Power Management chapter in the MCF52259 Reference Manual for more information on low-power modes. 3 CLKOUT, PST/DDATA signals, and all peripheral clocks except UART0 off before entering low-power mode. CLKOUT is disabled. Code executed from SRAM with flash memory shut off by writing 0x0 to the FLASHBAR register. 4 See the description of the Low-Power Control Register (LPCR) in the MCF52259 Reference Manual for more information on stop modes 0-3. 5 Results are identical to STOP 00 for typical values because they only differ by CLKOUT power consumption. CLKOUT is already disabled in this instance prior to entering low-power mode. 2.3 Thermal Characteristics Table 8. Thermal Characteristics Characteristic Symbol Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) -- -- Natural convection -- Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) -- -- Natural convection -- JA JA JMA JMA JB JC jt Tj JA JA JMA JMA JB JC jt Tj Value 531,2 301,3 431,3 261,3 164 95 26 105 447,8 351,9 351,3 29 1,3 Table 8 lists thermal resistance values. Unit C/W C/W C/W C/W C/W C/W C/W oC 144 MAPBGA Junction to ambient, natural convection Junction to ambient, natural convection Junction to ambient, (@200 ft/min) Junction to ambient, (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature 144 LQFP Junction to ambient, natural convection Junction to ambient, natural convection Junction to ambient, (@200 ft/min) Junction to ambient, (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature C/W C/W C/W C/W C/W C/W C/W oC 2310 711 2 12 105 MCF52259 ColdFire Microcontroller, Rev. 2 26 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics Table 8. Thermal Characteristics (continued) Characteristic 100 LQFP Junction to ambient, natural convection Junction to ambient, natural convection Junction to ambient, (@200 ft/min) Junction to ambient, (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature 1 Symbol Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) -- -- Natural convection -- JA JA JMA JMA JB JC jt Tj Value 5313,14 391,15 42 1,3 Unit C/W C/W C/W C/W C/W C/W C/W o 331,3 25 9 2 16 17 18 105 C JA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 2 Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. 3 Per JEDEC JESD51-6 with the board JESD51-7) horizontal. 4 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. 7 JA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 8 Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. 9 Per JEDEC JESD51-6 with the board JESD51-7) horizontal. 10 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 11 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 12 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. 13 JA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 14 Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. 15 Per JEDEC JESD51-6 with the board JESD51-7) horizontal. MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 27 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics 16 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 17 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 18 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. The average chip-junction temperature (TJ) in C can be obtained from: T J = T A + ( P D x JMA ) (1) Where: TA JA PD PINT PI/O = ambient temperature, C = package thermal resistance, junction-to-ambient, C/W = PINT + PI/O = chip internal power, IDD x VDD, watts = power dissipation on input and output pins -- user determined, watts For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is: P D = K / ( T J + 273C ) Solving equations 1 and 2 for K gives: K = PD x (TA + 273 C) + JMA x PD 2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. (2) 2.4 Flash Memory Characteristics Table 9. SGFM Flash Program and Erase Characteristics (VDD = 3.0 to 3.6 V) Parameter Symbol fsys(R) 2 The flash memory characteristics are shown in Table 9 and Table 10. Min 0 0.15 Typ -- -- Max 66.67 or 801 66.67 or 801 Unit MHz MHz System clock (read only) System clock (program/erase) 1 2 fsys(P/E) Depending on packaging; see the orderable part number summary. Refer to the flash memory section for more information Table 10. SGFM Flash Module Life Characteristics (VDD = 3.0 to 3.6 V) Parameter Maximum number of guaranteed program/erase cycles1 before failure Data retention at average operating temperature of 85C 1 Symbol P/E Retention Value 10,0002 10 Unit Cycles Years A program/erase cycle is defined as switching the bits from 1 0 1. MCF52259 ColdFire Microcontroller, Rev. 2 28 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics 2 Reprogramming of a flash memory array block prior to erase is not required. 2.5 Name EP1 EP1a EP2 EP3 EP4 EP5 EP6 EP7 EP8 EP9 EzPort Electrical Specifications Table 11. EzPort Electrical Specifications Characteristic EPCK frequency of operation (all commands except READ) EPCK frequency of operation (READ command) EPCS_b negation to next EPCS_b assertion EPCS_B input valid to EPCK high (setup) EPCK high to EPCS_B input invalid (hold) EPD input valid to EPCK high (setup) EPCK high to EPD input invalid (hold) EPCK low to EPQ output valid (out setup) EPCK low to EPQ output invalid (out hold) EPCS_B negation to EPQ tri-state Min -- -- 2 x Tcyc -- 5 -- 5 -- 0 -- Max fsys / 2 fsys / 8 -- 5 -- 2 -- 12 -- 12 Unit MHz MHz ns ns ns ns ns ns ns ns 2.6 ESD Protection Table 12. ESD Protection Characteristics1, 2 Characteristics ESD target for Human Body Model ESD target for Machine Model HBM circuit description Symbol HBM MM Rseries C MM circuit description Rseries C Number of pulses per pin (HBM) * Positive pulses * Negative pulses Number of pulses per pin (MM) * Positive pulses * Negative pulses Interval of pulses 1 Value 2000 200 1500 100 0 200 1 1 Units V V pF pF -- -- -- -- -- -- -- 3 3 1 sec All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 29 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics 2.7 DC Electrical Specifications Table 13. DC Electrical Specifications 1 Characteristic Symbol VDD VSTBY VIH VIL VHYS VLVD VLVDHYS Iin VOH VOL VOH VOL VOH VOL IAPU Cin -- -- 7 7 Min 3.0 1.8 0.7 x VDD VSS - 0.3 0.06 x VDD 2.15 60 -1.0 VDD - 0.5 -- VDD - 0.5 -- VDD - 0.5 -- -10 Max 3.6 3.5 4.0 0.35 x VDD -- 2.3 120 1.0 -- 0.5 -- 0.5 -- 0.5 -130 Unit V V V V mV V mV A V V V V V V A pF Supply voltage Standby voltage Input high voltage Input low voltage Input hysteresis Low-voltage detect trip voltage (VDD falling) Low-voltage detect hysteresis (VDD rising) Input leakage current Vin = VDD or VSS, digital pins Output high voltage (all input/output and all output pins) IOH = -2.0 mA Output low voltage (all input/output and all output pins) IOL = 2.0mA Output high voltage (high drive) IOH = -5 mA Output low voltage (high drive) IOL = 5 mA Output high voltage (low drive) IOH = -2 mA Output low voltage (low drive) IOL = 2 mA Weak internal pull Up device current, tested at VIL Max.2 Input Capacitance 3 * All input-only pins * All input/output (three-state) pins 1 2 Refer to Table 14 for additional PLL specifications. Refer to Table 3 for pins having internal pull-up devices. 3 This parameter is characterized before qualification rather than 100% tested. MCF52259 ColdFire Microcontroller, Rev. 2 30 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics 2.8 Clock Source Electrical Specifications Table 14. Oscillator and PLL Specifications (VDD and VDDPLL = 3.0 to 3.6 V, VSS = VSSPLL = 0 V) Characteristic Symbol fcrystal fext fref_pll fsys Min 0.5 0 2 0 fref / 32 100 1 -- 2.0 VSS -- 40 -1.5 -0.75 -- -- 7.84 Max 48.0 50.0 or 60.0 10.0 66.67 or 803 66.67 or 803 1000 5 0.1 VDD V 0.8 500 60 1.5 0.75 10 .01 8.16 s % fref % fref % fref % fsys MHz MHz MHz Unit MHz Clock Source Frequency Range of EXTAL Frequency Range * Crystal * External1 PLL reference frequency range System frequency 2 * External clock mode * On-chip PLL frequency Loss of reference frequency 4, 6 Self clocked mode frequency 5 Crystal start-up time 6, 7 fLOR fSCM tcst VIHEXT VILEXT tlpll tdc fUL fLCK Cjitter kHz MHz ms V EXTAL input high voltage * External reference EXTAL input low voltage * External reference PLL lock time4,8 Duty cycle of reference 4 Frequency un-LOCK range Frequency LOCK range CLKOUT period jitter 4, 5, 9 ,10, measured at fSYS Max * Peak-to-peak (clock edge to clock edge) * Long term (averaged over 2 ms interval) On-chip oscillator frequency 1 2 foco In external clock mode, it is possible to run the chip directly from an external clock source without enabling the PLL. All internal registers retain data at 0 Hz. 3 Depending on packaging; see the orderable part number summary. 4 Loss of Reference Frequency is the reference frequency detected internally, which transitions the PLL into self clocked mode. 5 Self clocked mode frequency is the frequency at which the PLL operates when the reference frequency falls below f LOR with default MFD/RFD settings. 6 This parameter is characterized before qualification rather than 100% tested. 7 Proper PC board layout procedures must be followed to achieve specifications. 8 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. 10 Based on slow system clock of 40 MHz measured at f sys max. MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 31 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics 2.9 USB Operation Table 15. USB Operation Specifications Characteristic Minimum core speed for USB operation Symbol fsys_USB_min Value 16 Unit MHz 2.10 Mini-FlexBus External Interface Specifications A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to interface to slave-only devices up to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface can be used. All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-FlexBus output clock (MB_CLK). All other timing relationships can be derived from these values. Table 16. Mini-FlexBus AC Timing Specifications Num Characteristic Frequency of Operation MB1 MB2 MB3 MB4 MB5 1 2 Min -- 12.5 -- 2 6 0 Max 80 -- 8 -- -- -- Unit MHz ns ns ns ns ns Notes Clock Period Output Valid Output Hold Input Setup Input Hold 1 1 2 2 Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE. Specification is valid for all MB_D[7:0]. MCF52259 ColdFire Microcontroller, Rev. 2 32 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics MB_CLK MB1 MB3 MB_A[19:X] MB2 A[19:X] MB5 MB_D[7:0] / MB_A[15:0] MB_R/W ADDRESS D[Y:0] MB4 MB3 MB2 MB_ALE MB_CSn MB2 MB3 MB_OE Figure 5. Mini-FlexBus Read Timing MB_CLK MB1 MB3 MB_A[19:X] MB2 A[19:X] MB_D[7:0] / MB_A[15:0] ADDRESS DATA[Y:0] MB_R/W MB3 MB2 MB_ALE MB_CSn MB2 MB3 MB_OE Figure 6. Mini-FlexBus Write Timing 2.11 Fast Ethernet Timing Specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 33 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics 2.11.1 Receive Signal Timing Specifications Table 17. Receive Signal Timing MII Mode The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices. Num -- E1 E2 E3 E4 1 Characteristic Min RXCLK frequency RXD[n:0], RXDV, RXER to RXCLK setup1 -- 5 5 35% 35% Max 25 -- -- 65% 65% Unit MHz ns ns RXCLK period RXCLK period RXCLK to RXD[n:0], RXDV, RXER hold1 RXCLK pulse width high RXCLK pulse width low In MII mode, n = 3 RXCLK (Input) E4 E3 E1 E2 RXD[n:0] RXDV, RXER Valid Data Figure 7. MII Receive Signal Timing Diagram 2.11.2 Transmit Signal Timing Specifications Table 18. Transmit Signal Timing MII Mode Num -- E5 E6 E7 E8 TXCLK frequency TXCLK to TXD[n:0], TXEN, TXER invalid TXCLK to TXD[n:0], TXEN, TXER valid1 TXCLK pulse width high TXCLK pulse width low 1 Characteristic Min -- 5 -- 35% 35% Max 25 -- 25 65% 65% Unit MHz ns ns tTXCLK tTXCLK 1 In MII mode, n = 3 TXCLK (Input) E6 E8 E7 E5 TXD[n:0] TXEN, TXER Valid Data Figure 8. MII Transmit Signal Timing Diagram MCF52259 ColdFire Microcontroller, Rev. 2 34 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics 2.11.3 Num E9 Asynchronous Input Signal Timing Specifications Table 19. MII Transmit Signal Timing Characteristic CRS, COL minimum pulse width Min 1.5 Max -- Unit TXCLK period CRS, COL E9 Figure 9. MII Async Inputs Timing Diagram 2.11.4 MII Serial Management Timing Specifications Table 20. MII Serial Management Channel Signal Timing Characteristic MDC cycle time MDC pulse width MDC to MDIO output valid MDC to MDIO output invalid MDIO input to MDC setup MDIO input to MDC hold E10 E11 Num E10 E11 E12 E13 E14 E15 Symbol tMDC Min 400 40 -- 25 10 0 Max -- 60 375 -- -- -- Unit ns % tMDC ns ns ns ns MDC (Output) E11 E12 E13 MDIO (Output) Valid Data E14 E15 MDIO (Input) Valid Data Figure 10. MII Serial Management Channel TIming Diagram 2.12 General Purpose I/O Timing GPIO can be configured for certain pins of the QSPI, DDR Control, timer, UART, Interrupt and USB interfaces. When in GPIO mode, the timing specification for these pins is given in Table 21 and Figure 11. The GPIO timing is met under the following load test conditions: * 50 pF / 50 for high drive MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 35 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics * 25 pF / 25 for low drive Table 21. GPIO Timing NUM G1 G2 G3 G4 Characteristic CLKOUT High to GPIO Output Valid CLKOUT High to GPIO Output Invalid GPIO Input Valid to CLKOUT High CLKOUT High to GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min -- 1.5 9 1.5 Max 10 -- -- -- Unit ns ns ns ns CLKOUT G1 G2 GPIO Outputs G3 G4 GPIO Inputs Figure 11. GPIO Timing 2.13 Reset Timing Table 22. Reset and Configuration Override Timing (VDD = 3.0 to 3.6 V, VSS = 0 V, TA = TL to TH)1 NUM R1 R2 R3 R4 1 2 Characteristic RSTI input valid to CLKOUT High CLKOUT High to RSTI Input invalid RSTI input valid time 2 Symbol tRVCH tCHRI tRIVT tCHROV Min 9 1.5 5 -- Max -- -- -- 10 Unit ns ns tCYC ns CLKOUT High to RSTO Valid All AC timing is shown with respect to 50% VDD levels unless otherwise noted. During low power STOP, the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to the system. Thus, RSTI must be held a minimum of 100 ns. CLKOUT 1R1 R2 R3 R4 R4 RSTI RSTO Figure 12. RSTI and Configuration Override Timing MCF52259 ColdFire Microcontroller, Rev. 2 36 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics 2.14 I2C Input/Output Timing Specifications Table 23. I2C Input Timing Specifications between I2C_SCL and I2C_SDA Num 11 I2 I3 I4 I5 I6 I7 I8 I9 Characteristic Start condition hold time Clock low period SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 x tCYC 8 x tCYC -- 0 -- 4 x tCYC 0 2 x tCYC 2 x tCYC Max -- -- 1 -- 1 -- -- -- -- Units ns ns ms ns ms ns ns ns ns Table 23 lists specifications for the I2C input timing parameters shown in Figure 13. Table 24 lists specifications for the I2C output timing parameters shown in Figure 13. Table 24. I2C Output Timing Specifications between I2C_SCL and I2C_SDA Num 111 I21 I32 I41 I5 3 Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 6 x tCYC 10 x tCYC -- 7 x tCYC -- 10 x tCYC 2 x tCYC 20 x tCYC 10 x tCYC Max -- -- -- -- 3 -- -- -- -- Units ns ns s ns ns ns ns ns ns I61 I7 1 I81 I91 1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 24. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 24 are minimum values. 2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 37 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics Figure 13 shows timing for the values in Table 23 and Table 24. I2 SCL I6 I5 I1 I4 I7 I8 I3 I9 SDA Figure 13. I2C Input/Output Timings 2.15 Analog-to-Digital Converter (ADC) Parameters Table 25. ADC Parameters1 Table 25 lists specifications for the analog-to-digital converter. Name VREFL VREFH VDDA VADIN RES INL INL DNL Characteristic Low reference voltage High reference voltage ADC analog supply voltage Input voltages Resolution Integral non-linearity (full input signal range)2 Integral non-linearity (10% to 90% input signal range)4 Differential non-linearity Monotonicity Min VSSA VDDA - 50 mV 3.1 VREFL 12 -- -- -- Typical -- -- 3.3 -- -- 2.5 2.5 -1 < DNL < +1 Max VSSA + 50 mV VDDA 3.6 VREFH 12 3 3 <+1 Unit V V V V Bits LSB3 LSB LSB GUARANTEED 0.1 VREFL -- -- 6 0 6 1 See Figure 14 See Figure 14 -- 0 8 1 3 5.0 VREFH 13 1 -- -- -- -- 3 -- 15 1.01 9 MHz V tAIC cycles6 tAIC cycles tAIC cycles tAIC cycles pF W mA mA mV -- mV fADIC RAD tADPU tREC tADC tADS CADI XIN IADI IVREFH VOFFSET EGAIN VOFFSET ADC internal clock Conversion range ADC power-up time 5 -- -- -- -- -- -- -- -- -- .99 -- Recovery from auto standby Conversion time Sample time Input capacitance Input impedance Input injection current7, per pin VREFH current Offset voltage internal reference Gain error (transfer path) Offset voltage external reference MCF52259 ColdFire Microcontroller, Rev. 2 38 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics Table 25. ADC Parameters1 (continued) Name SNR THD SFDR SINAD ENOB 1 2 3 4 5 6 7 Characteristic Signal-to-noise ratio Total harmonic distortion Spurious free dynamic range Signal-to-noise plus distortion Effective number of bits Min -- -- -- -- 9.1 Typical 62 to 66 -75 67 to 70.3 61 to 63.9 10.6 Max -- -- -- -- -- Unit dB dB dB dB Bits All measurements are preliminary pending full characterization, and made at VDD = 3.3V, VREFH = 3.3V, and VREFL = ground INL measured from VIN = VREFL to VIN = VREFH LSB = Least Significant Bit INL measured from VIN = 0.1VREFH to VIN = 0.9VREFH Includes power-up of ADC and VREF ADC clock cycles Current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC 2.16 Equivalent Circuit for ADC Inputs Figure 10-17 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and hold circuit moves to (VREFH-VREFL)/2, while the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended analog input is switched to a differential voltage centered about (VREFH-VREFL)/2. The switches switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). There are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, VREF and the ADC clock frequency. 125W ESD Resistor 8pF noise damping capacitor Analog Input 3 S1 4 C1 S3 S/H C2 C1 = C2 = 1pF 1 2 (VREFH- VREFL)/ 2 S2 1. 2. 3. 4. 5. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF Equivalent resistance for the channel select mux; 100 s Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only connected to it at sampling time; 1.4pF 1 Equivalent input impedance, when the input is selected = (ADC Clock Rate) x (1.4x10-12) Figure 14. Equivalent Circuit for A/D Loading MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 39 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics 2.17 DMA Timers Timing Specifications Table 26. Timer Module AC Timing Specifications Name T1 T2 Characteristic1 DTIN0 / DTIN1 / DTIN2 / DTIN3 cycle time DTIN0 / DTIN1 / DTIN2 / DTIN3 pulse width Min 3 x tCYC 1 x tCYC Max -- -- Unit ns ns Table 26 lists timer module AC timings. 1 All timing references to CLKOUT are given to its rising edge. 2.18 QSPI Electrical Specifications Table 27. QSPI Modules AC Timing Specifications Table 27 lists QSPI timings. Name QS1 QS2 QS3 QS4 QS5 QSPI_CS[3:0] to QSPI_CLK Characteristic Min 1 -- 2 9 9 Max 510 10 -- -- -- Unit tCYC ns ns ns ns QSPI_CLK high to QSPI_DOUT valid QSPI_CLK high to QSPI_DOUT invalid (Output hold) QSPI_DIN to QSPI_CLK (Input setup) QSPI_DIN to QSPI_CLK (Input hold) The values in Table 27 correspond to Figure 15. QS1 QSPI_CS[3:0] QSPI_CLK QS2 QSPI_DOUT QS3 QSPI_DIN QS4 QS5 Figure 15. QSPI Timing 2.19 JTAG and Boundary Scan Timing MCF52259 ColdFire Microcontroller, Rev. 2 40 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics Table 28. JTAG and Boundary Scan Timing Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 1 Characteristics1 TCLK frequency of operation TCLK cycle period TCLK clock pulse width TCLK rise and fall times Boundary scan input data setup time to TCLK rise Boundary scan input data hold time after TCLK rise TCLK low to boundary scan output data valid TCLK low to boundary scan output high Z TMS, TDI input data setup time to TCLK rise TMS, TDI Input data hold time after TCLK rise TCLK low to TDO data valid TCLK low to TDO high Z TRST assert time TRST setup time (negation) to TCLK high Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST Min DC 4 x tCYC 26 0 4 26 0 0 4 10 0 0 100 10 Max 1/4 -- -- 3 -- -- 33 33 -- -- 26 8 -- -- Unit fsys/2 ns ns ns ns ns ns ns ns ns ns ns ns ns JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing. J2 J3 J3 TCLK (input) J4 VIH VIL J4 Figure 16. Test Clock Input Timing MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 41 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics TCLK VIL J5 VIH J6 Data Inputs J7 Input Data Valid Data Outputs J8 Output Data Valid Data Outputs J7 Data Outputs Output Data Valid Figure 17. Boundary Scan (JTAG) Timing TCLK VIL J9 VIH J10 TDI TMS J11 Input Data Valid TDO J12 Output Data Valid TDO J11 TDO Output Data Valid Figure 18. Test Access Port Timing TCLK 14 TRST 13 Figure 19. TRST Timing MCF52259 ColdFire Microcontroller, Rev. 2 42 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics 2.20 Debug AC Timing Specifications Table 29. Debug AC Timing Specification 66/80 MHz Num D1 D2 D3 D41 D5 D6 D7 D8 1 Table 29 lists specifications for the debug AC timing parameters shown in Figure 21. Characteristic Min PST, DDATA to CLKOUT setup CLKOUT to PST, DDATA hold DSI-to-DSCLK setup DSCLK-to-DSO hold DSCLK cycle time BKPT input data setup time to CLKOUT rise BKPT input data hold time to CLKOUT rise CLKOUT high to BKPT high Z 4 1.5 1 x tCYC 4 x tCYC 5 x tCYC 4 1.5 0.0 Max -- -- -- -- -- -- -- 10.0 Units ns ns ns ns ns ns ns ns DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT. Figure 20 shows real-time trace timing for the values in Table 29. CLKOUT D1 D2 PST[3:0] DDATA[3:0] Figure 20. Real-Time Trace AC Timing MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 43 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Electrical Characteristics Figure 21 shows BDM serial port AC timing for the values in Table 29. CLKOUT D5 DSCLK D3 DSI Current D4 DSO Past Current Next Figure 21. BDM Serial Port AC Timing 3 Package Information The latest package outline drawings are available on the product summary pages on http://www.freescale.com/coldfire. Table 30 lists the case outline numbers per device. Use these numbers in the web page's keyword search engine to find the latest package outline drawings. Table 30. Package Information Device MCF52252 MCF52254 MCF52255 MCF52256 MCF52258 MCF52259 144 LQFP or 144 MAPBGA 98ASS23177W 98ASH70694A 100 LQFP 98ASS23308W Package Type Case Outline Numbers MCF52259 ColdFire Microcontroller, Rev. 2 44 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Package Information 4 Revision History Table 31. Revision History Revision 0 1 Initial public release. * Added package dimensions to package diagrams * Added listing of devices for MCF52259 family * Changed "Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width modulation (PWM), and pulse accumulation" to "Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width modulation (PWM), pulse-code modulation (PCM), and pulse accumulation" * Updated the figure Pinout Top View (144 MAPBGA) * Removed an extraneous instance of the table Pin Functions by Primary and Alternate Purpose * In the table Pin Functions by Primary and Alternate Purpose, changed a footnote from "This list for power and ground does not include those dedicated power/ground pins included elsewhere, such as in the ADC" to "This list for power and ground does not include those dedicated power/ground pins included elsewhere, such as in the ADC, USB, and PLL" * In the table SGFM Flash Program and Erase Characteristics, changed "(VDDF = 2.7 to 3.6 V)" to "(VDD = 3.0 to 3.6 V)" * In the table SGFM Flash Module Life Characteristics, changed "(VDDF = 2.7 to 3.6 V)" to "(VDD = 3.0 to 3.6 V)" * In the table Oscillator and PLL Specifications, changed "VDD and VDDPLL = 2.7 to 3.6 V" to "VDD and VDDPLL = 3.0 to 3.6 V" * In the table Reset and Configuration Override Timing, changed "VDD = 2.7 to 3.6 V" to "VDD = 3.0 to 3.6 V" * Added EzPort Electrical Specifications. * Updated Table 2 for part numbers. * In Table 3, added slew rate column, updated derive strength, pull-up/pull-down values,JTAG pin alternate functions, removed Wired/OR control column, and reordered AN[7:0] list of pin numbers for 144 LQFP and 100 LQFP. * Updated Table 14. * Updated Table 13, to change MIN voltage spec for Standby Voltage (VSTBY) to 1.8V (from 3.0V). * Updated Figure 2 for RTC_EXTAL and RTC_XTAL pin positions. Description 2 MCF52259 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 45 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages Revision History How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com Freescale Semiconductor Literature Distribution Center 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2009. All rights reserved. Document Number: MCF52259 Rev. 2 8/2009 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages |
Price & Availability of MCF52268AG80
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |